1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an OTP memory including so-called antifuse devices as memory cells.
2. Description of the Related Art
In semiconductor integrated circuits, non-volatile one-time programmable (OTP) memories are essential elements in which no stored data is lost even when the power supply is turned off. The OTP memories are used in a wide range of applications such as redundancies for large-capacity memories such as DRAM and SRAM, tuning of analog circuits, and storing codes such as cipher keys.
One of the conventional OTP memories that have mainly been used is a laser fuse ROM. The laser fuse ROM includes a laser fuse that irreversibly stores information using a laser light blow. The laser fuse ROM requires, however, a special fuse-blow device and a blow process using the device, causing a problem of much test cost. The laser fuse has a problem that its minimum dimension depends on the wavelength of the laser light, so the laser fuse cannot be reduced in dimension falling into step with the other circuit portions and has come to occupy a larger area than the others. The programming method of the laser fuse enables only a wafer-level programming, thus making it hard to perform processes such as fault-segment recovery in a high-speed test after packaging and a built-in self-repair by test circuits mounted in a chip.
As another aspect of the OTP memory, a memory including a so-called gate dielectric film breakdown antifuse device as a memory element is proposed (see, for example, H. Ito et al. “Pure CMOS One-time Programmable Memory using Gate-OX Antifuse”, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, PP. 469-472). The antifuse device can have data written thereto by breakdown of the gate dielectric film of the MOS transistor by application of a high voltage. The antifuse device can also hold data according to the difference of currents through the gate dielectric film due to the presence or absence of the film breakdown. The antifuse device can thus eliminate an additional special process, thereby facilitating mount of the device on a system-on-chip (SoC) where a system is integrated on a chip.
In the OTP memories including the antifuse devices, as MOSFETs become smaller decreasing the gate dielectric film thicknesses, the gate-leak currents in the antifuse devices increase. This reduces the read margin and causes misreading. Specifically, the variation of the gate dielectric film thickness and the variation of the impurity concentration or defect density in the gate dielectric film or the like cause a large variation of the gate-leak current in a large number of memory cells in the OTP memories that include the antifuse devices. An exceptionally large gate-leak current generated even in a very small number of memory cells of a large number of memory cells will reduce the read margin of “0”, increasing the possibility that “0” is misread as “1.” This will cause the problem of lower yield and reliability.
It is hard to deal with the above problems from an aspect of manufacturing processes. This is because the logic circuits mounted on the same chip will not suffer significant disadvantages from some gate-leak current, so addressing the manufacturing process may affect on the characteristics of the logic circuit transistors. Other measures such as error correction circuits may be possible, but the correction circuits will increase the chip area, inevitably increasing the cost.